This invention relates to bubble memories, and more particularly to methods and apparatus for dealing with defective minor loops in the memory. Presently, the most popular architecture for a bubble memory includes a plurality of minor loops for storing bubbles representative of data therein. The bubbles are written into these minor loops and read therefrom in response to control signals applied to the memory. However, due to a variety of reasons, a small number of the loops, such as five or ten percent, typically are defective. These defects may be due to flaws in the garnet film in which the bubbles are formed. They may also be due for example, to permalloy defects arising from dust which enter the memory during the lithography stage of its fabrication.
Thus, in order to construct high yield bubble memory chips, it is necessary to provide extra minor loops on the chip. Then, during final chip testing, the defective loops are determined; and this information is subsequently used to control which loops are actually used to store bubbles.
In the prior art, defective loops were identified to the user by stamping a defective loop may on each of the chips. The user would then encode this information into a read only memory (ROM). And the ROM was then used in conjunction with other control logic to mask out the defective loops during a write or read operation.
More recently, some bubble memories have included a single extra loop on the chip for storing error map information therein. The user is thus able to read the error map from the memory during system initialization and store that map in a RAM. The RAM is then used in conjunction with control logic to mask out the defective loops during a write or read operation.
Both of the above approaches however, have certain deficiencies. For example, with ROM approach, each memory system requires unique parts. That is, the ROM for one memory system cannot be used as the ROM in another memory system because the bubble memory chips in each memory system have a different defective minor loops. Further, when a bubble chip in a memory system goes completely bad, due to aging for example, the replacement of the bubble chip also necessitates the replacement of the ROM.
Similarly, one problem with the prior art bubble memory chips that provide an on-chip error map is that they include no redundant error map loops. That is, they include only a single error map loop. Therefore, if that loop is defective, due to any of the above described processing problems, then the entire chip must be discarded. Thus, the production yield of those bubble memory chips is undesirably low.
It is therefore desirable to provide redundant error map loops on the bubble memory chip. However, this raises the question of how the redundant error map loops can be selectively written into and read from. Clearly, one approach is to provide separate transfer-in control lines and separate replicate-out/transfer-out control lines for each of the redundant loops. However, the problem with that approach is that it takes too many pins. For example, two error map loops having separate input and output control lines require eight extra pins; and these pins in combination with the pins required to operate the data storage loops would make the chip prohibitively large.
Therefore, it is one object of the invention to provide an improved bubble memory chip having redundant error map storage loops with selection controls that do not require a prohibitive number of extra pins.
Another object of the invention is to provide a bubble memory chip having two redundant error map loops that are separately selectable with only two extra pins.